1. Technical Field
The present invention relates generally to electronic interface operation, and more particularly, to interfaces that are tested for fault detection and calibration prior to and/or during operation.
2. Description of the Related Art
Interfaces between present-day integrated circuits have increased in operating frequency and width. In particular, multiprocessing systems, where multiple processors are arranged in an array or a cube, both wide and fast connections are provided between many processing units. Data width directly affects the speed of data transmission between systems components, as does the data rate, which is limited by the maximum frequency that can be supported by an interface.
Present-day systems interconnect designs use transmission line techniques to improve signal transmission/reception. Low voltage and current signaling levels are desirable to reduce driver size, power consumption/dissipation and electromagnetic interference (EMI). The interface schemes used for the above-mentioned interconnect designs are incorporating an increasing amount of intelligence and flexibility, along with incorporating the consequent circuit complexity to support these features. In particular, interfaces such as those disclosed in U.S. Patent Application “ELASTIC INTERFACE APPARATUS AND METHOD THEREFOR”, publication number US2002/0013875A1, incorporated herein by reference, discloses an exemplary interface that can synchronize asynchronously transmitted data streams between two interconnected subsystems. An interface alignment procedure (IAP) is performed at initialization and optionally dynamically during operation in order to maintain optimum synchronization, which reduces the bit error rate (BER) of the interface.
Interfaces such as the EI described above, especially when incorporated within multiprocessing systems where errors from a single unit can corrupt operation and data within the entire system, employ sophisticated initialization test procedures that, in addition to the IAP mentioned above, are used to verify proper DC (static) and AC (dynamic) operation of the interface prior to and optionally during operation of the system. Failure of the DC and AC tests due to an interface fault is typically used to disable the interface and generate an interface failure indication. Recalibration procedures and initial calibration such as IAP are typically not performed on interfaces that do not pass initial wire test, as the interface is not used subsequent to detecting a failure. A recalibration procedure could also enter a fail state or otherwise generate an erroneous setting if performed on an interface connection that has one or more faulty bits. U.S. Patent Application “METHOD AND APPARATUS FOR ELASTIC SHORTS TESTING, A HARDWARE-ASSISTED WIRE TEST MECHANISM”, publication number. US2002/0078402A1, describes a wire test mechanism and U.S. patent application “DATA PROCESSING SYSTEM AND METHOD WITH DYNAMIC IDLE FOR TUNABLE INTERFACE CALIBRATION”, Ser. No. 09/946,217 filed Sep. 5, 2001, describes a periodic recalibration of an EI. The above-referenced patent applications are incorporated herein by reference.
Present-day high-speed interfaces such as the Elastic Interface (EI) of the above-incorporated patent applications typically may further include error checking and correcting (ECC) circuitry that provides tolerance to at least single-bit errors on the interface by correcting single-bit errors on-the-fly. A tradeoff between the number of bits required to detect and correct errors versus the data width typically renders a choice for interface hardware connections of double-bit detection and single-bit correction, but “stronger” ECC may also be employed at the expense of additional interface bit width. Such ECC circuitry is used to correct transient errors on an interface, but will also provide proper interface operation for a failure of a number of interface connections that is less than or equal to the ECC correction capacity, if the failure(s) occur(s) subsequent to initialization of the interface, and if dynamic recalibration is not employed.
It is therefore desirable to provide a method and apparatus for surviving interface failures that takes advantage of correction of correctable errors. It is further desirable to provide a method and apparatus for surviving interface failures that occur prior to and subsequent to interface initialization.